• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to a method of manufacturing a structure comprising the following successive steps: - providing a so-called high resistivity silicon support substrate (2) comprising a lower part and an upper part (3) having undergone a p-type doping on a depth D; forming a mesoporous layer (1) of silicon in the doped upper part (3) of the support substrate (2); forming a dielectric layer (6) on the mesoporous layer of silicon (1); - forming a semiconductor layer (7) on the dielectric layer (6); the manufacturing method being characterized in that, before forming the dielectric layer (6), the mesoporous layer (1) of silicon is obtained by a process of electrolysis of the doped upper part (3) of the support substrate (2) of high resistivity silicon according to a predetermined porosity rate.
    公开号:FR3024587A1
    申请号:FR1401800
    申请日:2014-08-01
    公开日:2016-02-05
    发明作者:Den Daele William Van；Oleg Kononchuk
    申请人:Soitec SA；
    IPC主号:
    专利说明:

    [0001] The present invention relates to a structure comprising successively a so-called high-resistivity (HR) silicon support substrate, a mesoporous silicon layer, a dielectric layer and a semiconductor layer, for example intended to be used in the manufacture of high frequency applications (HF). BACKGROUND OF THE INVENTION The method according to the invention is particularly suitable for the manufacture of HF applications, that is to say higher than 100 MHz, such as a radiofrequency (RF) application for integrated circuits with an operating frequency whose order of magnitude is a few GHz. For this purpose, such a structure must have a high electrical resistivity, that is to say greater than 5 KI.cm, at least in the vicinity of the active semiconductor layer on which or in which the integrated circuits will be formed. . This type of structure is in particular known from document FR 2 967 812. However, this document remains silent as to the characteristics of the support substrate and of the porous silicon layer in order to maximize the electrical resistivity of the structure while maintaining a satisfactory mechanical strength. . The mechanical strength can be defined by the ability to survive a manufacturing process with a probability of 1, or for example that less than 30 ppm of the plate breaks. The present invention is applicable, for example, to so-called eSi (Enhanced Signal Integrity) substrates for the manufacture of high performance radio frequency (RF) circuits at a competitive cost. Innovative and based on Smart Cut (TM) technology, eSI substrates have a significant impact on the performance of end products. They are obtained by introducing a layer, commonly called "trap-rich", between the highly resistive layer (HR) of a silicon support substrate and a buried dielectric layer. This layer limits the surface parasitic conduction present in the silicon support substrate HR, improving the performance of the RF circuits. RF circuits can thus integrate various functions, such as switches, power amplifiers, antenna tuners, .... The eSI substrate provides excellent RF isolation, low insertion loss, better thermal conductivity, and better signal integrity compared to other technologies. The processes for manufacturing eSi substrates are aimed at producing a structure comprising successively a so-called high-resistivity (HR) silicon support substrate, a so-called trap-rich silicon porous layer, a dielectric layer and a semiconductor layer. The porous layer is usually a layer of polysilicon epitaxially deposited on the silicon substrate support HR. Such a solution generates various types of problems in particular: the poly-silicon recrystallizes during a subsequent thermal step 20 thus contributing to decrease the density of the traps in the poly-silicon layer, and thus to reduce its resistivity; the known methods for depositing the poly-silicon layer do not make it possible to obtain a perfectly uniform surface, which then requires an additional step, for example, of CMP. The deposition of the porous layer does not make it possible to obtain a very thin layer thickness, less than 1 μm. The porosity ratio and the thickness of the porous layer contribute to defining the mechanical strength of the porous layer then manufacturing states. Thus, the thicker a porous layer, the lower its mechanical strength, and vice versa. Thus, the porous layers and their thickness, between 10 μm and 80 μm, of the prior art do not make it possible to obtain a layer with sufficient mechanical strength. Finally, the solutions of the prior art, integrating so-called high resistivity (HR) silicon substrates, show a harmonic distortion resulting from electrical losses of a silicon substrate on which RF circuits are arranged. These electrical losses help to degrade the performance of the structure (see the "Silicon-on-insulator (SOI) Technology, Manufacture and Applications" doctrine, points 10.7 and 10.8, Oleg Kononchuk and Bich-Yen Nguyen, Woodhead Publishing). Thus, the solutions of the prior art do not allow to obtain a porous layer with sufficient mechanical strength, a reduced level of electrical losses, and providing a structure with a high and controlled resistivity level.
    [0002] The present invention aims to obtain a structure obviating the problems of the prior art. OBJECT OF THE INVENTION To this end, the present invention relates to a method of manufacturing a structure comprising the following successive steps: - providing a so-called high resistivity silicon support substrate having a lower portion and an upper portion having doped with type p on a depth D; forming a mesoporous layer of silicon in the doped upper part of the support substrate; forming a dielectric layer on the mesoporous silicon layer; forming a semiconductor layer on the dielectric layer.
    [0003] Prior to forming the dielectric layer, the mesoporous silicon layer is obtained by a method of electrolysis of the doped top portion of the high resistivity silicon support substrate at a predetermined porosity level. The Applicant has found that the porosity of the mesoporous layer thus obtained allows to precisely control the level of resistivity of the structure, and can be high (> 5 kû.cm). Moreover, the adjustment of the porosity ratio, according to a range of precise values (between 20% and 60%), and the depth D (less than 1 μm) of the doping of the upper part of the so-called high silicon support substrate. resistivity allow, after the electrolysis process performed, to ensure a good mechanical strength of the mesoporous layer, a level of electrical losses of the reduced structure, as well as properties of resistivity and radiofrequency insulation (RF) performance. Furthermore, the electrolysis process of the silicon support substrate makes it possible to manufacture a very thin mesoporous layer (less than 1 μm) in a simple and effective manner, and to avoid the deposition of a mesoporous layer on the support substrate, thus avoiding the time of realization and the problems related to the steps of planarization, etchings and / or finishes necessary for the deposit of a substrate on another.
    [0004] BRIEF DESCRIPTION OF THE DRAWINGS The invention will be better understood in the light of the following description of the particular and nonlimiting embodiment of the invention with reference to the attached figures among which: FIG. 1 is a diagrammatic view in cross-section of a support substrate; - Figure 2 is a schematic cross-sectional view of the support substrate having undergone electrolysis; FIG. 3 is a graph showing the dependence of the Young's modulus with the porosity of the silicon; FIG. 4 is a graph showing the evolution of p-type dopant element as a function of the depth in the support substrate; - Figure 5 is a schematic cross-sectional view of a structure according to the invention. DETAILED DESCRIPTION OF AN EMBODIMENT One of the possible embodiments of the manufacturing method according to the invention, and making it possible to overcome the previously mentioned problems, will now be described with reference to FIGS. 1 to 5. manufacture of a structure according to the invention aims to control the thickness and the porosity rate of a mesoporous layer 1 contained in a high resistivity silicon support substrate 2, and 25, to obtain a structure having a specific resistivity and predetermined, good mechanical strength, and a reduction of electrical losses of the structure. To do this, the high-resistivity silicon substrate 2 (HR), shown in FIG. 1, undergoes p-type surface doping on an upper part 3 and a predetermined depth D of the silicon support substrate HR 2. The doping of the upper part 3 of the silicon substrate HR 2 may be carried out by any technique known from the prior art, such as ion implantation followed by RTA annealing to activate the p-type dopants, epitaxy of a p + layer, Spin on glass doping,. Thus doped, the upper part 3 of the silicon support substrate HR 2 is then subjected to an electrolysis process, so as to modify the upper part 3 of the silicon support substrate HR 2 in a porous layer 1, illustrated in FIG. and more particularly a mesoporous layer 1 having pores 4 with a diameter of between 2 nm and 50 nm. The depth D of doping elements introduced into the silicon support substrate HR 2 corresponds to the depth of the mesoporous layer 1. Thus, the mesoporous layer of silicon 1 constitutes a surface area of the silicon support substrate HR 2. One embodiment such a process may be an electrochemical anodization, wherein at least the upper portion 3 of the silicon support substrate HR 2 is placed in an enclosure comprising an electrolyte, such as hydrofluoric acid. An anode and a cathode are then immersed in the electrolyte and fed by a source of electric current, not shown. The Applicant has found that the initial resistivity of the HR silicon support substrate, as well as the morphology of the porous silicon had a considerable influence on the electrical resistivity and on its mechanical strength of the structure. There are three types of morphology for porous silicon: macroporous silicon, generally obtained from low doped n-type silicon and having a pore diameter greater than 50 nm; mesoporous silicon, generally obtained from highly doped p-type silicon, and having a pore diameter of between 2 nm and 50 nm; nanoporous silicon (or also called microporous silicon), generally obtained from p-type silicon which is slightly doped, and having a pore diameter of less than 2 nm. In general, in order for the electrolysis process to work, thus making it possible to obtain a porous silicon layer on the basis of an HR silicon support substrate, the support substrate 10 made of silicon HR must comprise doping agents. type p. Depending on the doping level of the substrate and the conditions of the electrolysis process, such as the adjustment of the electrical current density applied by the electric power source, the porosity rate will be greater or lesser and controlled. The porosity Po of a layer is defined as the fraction of unoccupied volume within the layer, and is written: Po = (d-dPo) / d where d is the density of the non-porous material and dPo is the density of the porous material. For example, in the case of an undoped HR type silicon substrate, the holes are in very low concentration (Na = 2e13 cm-3) and the porosification process causes, under standard electrolysis conditions, the creating empty macropores. In order to increase the level of p-type dopants in the HR support substrate, a prior art solution is to illuminate the HR silicon support substrate during the porosification process to create pairs of electron holes in the substrate. structure. A macroporous but nanoporous layer with pore diameters of less than 2 nm and a high porosity (P> 75%) equivalent to a standard porosification of a very highly doped substrate (Na> 2e19 cm-3) are then obtained. ). The porosity of the layer thus obtained then has a porosity rate sufficient to obtain a high level of resistivity. However, such porosity levels generate a lack of mechanical strength of the porous layer, and especially when the porous layer is thick, greater than 1 .mu.m. Thus, the thickness and the porosity ratio of said layer contribute to characterize the mechanical strength of the porous layer.
    [0005] FIG. 3 represents the dependence of the Young's modulus with respect to the porosity ratio of the mesoporous layer 3. For a given thickness, the higher the porosity ratio, the lower the mechanical properties of said layer 3. On the other hand, because of the porosity ratio and the weight of the porous layer, the thicker the porous layer, the lower the mechanical properties of said layer. Thus, for the structure according to the invention to develop a resistivity and sufficient mechanical strength, for example for the realization of a Smart Cut type process in the context of the manufacture of substrates called eSi (Enhanced Signal Integrity), the Mesoporous layer 1, according to the invention, advantageously has a porosity level Po of between 20% and 60% and a thickness of less than 1 μm. Thus, the thickness D of the mesoporous layer 1 depends on the depth of the p-type doping, and the porosity rate depends on the quantity of dopant elements introduced into the upper part 3 of the silicon substrate HR 2 and the conditions implementation of the electrolysis process. In order to ensure that the porosification by electrolysis of the upper portion 3 of the silica support substrate HR 2 does not exceed the predetermined depth D, a voltage monitoring is set up across the electrolysis, making it possible to determine when the porosification begins in the undoped HR 2 silicon substrate support, and thus stop the electrolysis process. As shown in FIG. 4, the porosification of the upper portion 3 of the silicon support substrate HR 2 must stop at the end of the dopant diffusion tail 5, so that the porosity of the silicon support substrate HR 2 is less than that of the mesoporous layer 1. Thus, the manufacturing method according to the invention makes it easy to produce the mesoporous layer 1 in a thickness D, ideally less than 1 micron, and a porosity level of between 20% and 60%, depending on the specific needs of a given industrial situation. Such a method therefore makes it possible to prevent the deposition of a mesoporous layer on the HR 2 silicon support substrate, which can generate various technical problems to be solved, but also to ensure good mechanical strength of the mesoporous layer 1, as well as high resistivity and radiofrequency (RF) insulation properties for the structure, and a reduction in the electrical losses of the structure. Even if the mechanical strength would be insufficient for the specific technical needs of a future step, not described, of a manufacturing process, a layer, for example, of SiN can be formed in order to increase the rigidity of the mesoporous layer and / or ensure a good temperature resistance of the assembly. Once the electrolysis process has been performed, a dielectric layer 6 is formed on the mesoporous layer 1. The dielectric layer 6 may be selected from silicon dioxide, silicon oxynitride or silicon nitride.
    [0006] A semiconductor layer 7 is then formed on the dielectric layer 6. The semiconductor layer may be selected according to one of the materials selected from the group consisting of Si, Ge, IV-IV materials such as Si-Ge, III-V materials such as Gan, GaAs, InP, InGasAs, matervax II-VI.
    [0007] The term "dielectric layer" and "semiconductor layer" means a single layer or several sub-layers of the same nature. Naturally, the invention is not limited to the embodiment described. Alternative embodiments can be made without departing from the scope of the invention, as defined by the claims. Thus, the method of manufacturing a structure according to the invention makes it possible to control the thickness and the desired porosity rate of the mesoporous layer 1 with respect to desired characteristics, and thus to obtain a mechanical strength of the mesoporous layer 1 sufficient, control the level of resistivity of the structure, and facilitate the manufacture of such a structure.
    权利要求:
    Claims (7)
    [0001]
    REVENDICATIONS1. A method of manufacturing a structure comprising the following successive steps: - providing a so-called high resistivity silicon support substrate (2) comprising a lower part and an upper part (3) having undergone p-type doping to a depth D; forming a mesoporous layer (1) of silicon in the doped upper part (3) of the support substrate (2); forming a dielectric layer (6) on the mesoporous layer of silicon (1); - forming a semiconductor layer (7) on the dielectric layer (6); the manufacturing method being characterized in that, before forming the dielectric layer (6), the mesoporous layer (1) of silicon is obtained by a process of electrolysis of the doped upper part (3) of the support substrate (2) of high resistivity silicon according to a predetermined porosity rate.
    [0002]
    2. The manufacturing method according to claim 1, wherein the mesoporous layer (1) of silicon has a porosity of between 20% and 60%.
    [0003]
    3. The manufacturing method according to claim 1, wherein the depth D is less than lpm.
    [0004]
    4. The manufacturing method according to claim 1, wherein the electrolysis process of the support substrate (2) of high resistivity silicon is controlled by a so-called voltage monitoring technique at the terminals of the electrolysis.
    [0005]
    5. The manufacturing method according to claim 1, wherein a SiN layer is deposited between the mesoporous layer of silicon (1) and the dielectric layer (6).
    [0006]
    The manufacturing method according to claim 1, wherein the dielectric layer (6) is selected from the group consisting of silicon dioxide, silicon oxynitride or silicon nitride.
    [0007]
    The manufacturing method according to claim 1, wherein the semiconductor layer (7) is made of a material selected from the group consisting of Si, Ge, IV-IV materials such as Si-Ge, III-V materials. such as Gan, GaAs, InP, InGasAs, the matervax
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    法律状态:
    2015-07-27| PLFP| Fee payment|Year of fee payment: 2 |
    2016-02-05| PLSC| Publication of the preliminary search report|Effective date: 20160205 |
    2016-07-20| PLFP| Fee payment|Year of fee payment: 3 |
    2017-07-20| PLFP| Fee payment|Year of fee payment: 4 |
    2018-07-20| PLFP| Fee payment|Year of fee payment: 5 |
    2019-07-22| PLFP| Fee payment|Year of fee payment: 6 |
    2020-07-21| PLFP| Fee payment|Year of fee payment: 7 |
    2021-07-27| PLFP| Fee payment|Year of fee payment: 8 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1401800|2014-08-01|
    FR1401800A|FR3024587B1|2014-08-01|2014-08-01|METHOD FOR MANUFACTURING HIGHLY RESISTIVE STRUCTURE|FR1401800A| FR3024587B1|2014-08-01|2014-08-01|METHOD FOR MANUFACTURING HIGHLY RESISTIVE STRUCTURE|
    US15/500,721| US10347597B2|2014-08-01|2015-07-03|Structure for radio-frequency applications|
    SG10201900450PA| SG10201900450PA|2014-08-01|2015-07-03|Structure for radio-frequency applications|
    PCT/FR2015/051854| WO2016016532A1|2014-08-01|2015-07-03|Structure for radio-frequency applications|
    SG11201700606YA| SG11201700606YA|2014-08-01|2015-07-03|Structure for radio-frequency applications|
    JP2017505533A| JP6643316B2|2014-08-01|2015-07-03|Structure of radio frequency application|
    KR1020177002895A| KR20170038819A|2014-08-01|2015-07-03|Structure for radio-frequency applications|
    EP15742368.2A| EP3175477B1|2014-08-01|2015-07-03|Structure for radio-frequency applications|
    CN201580041382.5A| CN106575637B|2014-08-01|2015-07-03|Structure for radio frequency applications|
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